1. Field of the Invention
The invention pertains to the field of packaging solid state devices. More particularly, the invention pertains to packaging high power solid state devices used to control high voltage, high current, or both high voltage and high current, in areas such as pulsed power for electromagnets, lasers, ion sources, X-ray sources, and other applications.
2. Description of Related Art
Packaging of high power solid state devices, such as diodes, transistors, and thyristors, has to encompass the interconnection of the devices and external contacts, heat dissipation for up to hundreds of watts of heat, and electrical insulation for up to thousands of volts. Typically, these packages include a base, such as a ceramic substrate, solid state devices, wires and other metal contacts connected to the base and the solid state devices, a shell, and encapsulant. Several steps are necessary to assemble these packages. The solid state device and required metal contacts are soldered to the base. The wires are soldered to the base and to the solid state device. The assembly of the base, solid state device, wires, and metal contacts, is placed in a shell. The shell is filled with an encapsulant. An example can be seen in U.S. Pat. No. 6,597,585, which describes a method using a plastic housing and a ceramic substrate. Another example of such packaging methods can be seen in U.S. Pat. No. 6,597,063, describing a packaging method with an integrated heat sink.
This method of packaging is easy for single device modules or simple solid state devices. As the number of interconnections increases, the assembly of the package becomes more difficult. Examples of the increases in complexity include connecting to the gate of a thyristor, or with multiple devices, the interconnection of devices in parallel or in series. An invention describing a packaging method for these more complicated systems can be seen in U.S. Pat. No. 6,566,750, although this packaging method is for a non-insulated power semiconductor module. Another example can be seen in U.S. Pat. No. 6,627,987, in which a packaging method using pockets in a ceramic substrate is described.
U.S. Pat. Application No. 20030205804 describes the manufacture of such packages using a ceramic base and a thin-film circuit layer for the interconnections. This method replaces the wires and other metal contacts used for interconnections with a thin-film circuit layer, significantly reducing problems associated with assembling wires and other metal contacts in these packages. The advances in creating thin-film circuit layers using deposition and lithography techniques developed for semiconductor manufacturing allow this procedure to easily interconnect complex packages of solid state devices. However, such methods increase the cost in time and material.
Whatever method is used to package high power solid state devices, it is important to consider electrical insulation, impedance, and inductance. The package has to insulate above the maximum operating voltage to prevent breakdown and shorting, resulting in damage to the package. Selecting appropriate insulating material is important. Also, the impedance of the electrical connections internal and external to the package must be kept as low as possible to prevent power loss and additional heating in those connections. Power loss reduces efficiency while heating can cause localized stress. Lastly, the inductance of the interconnections must also be kept as low as possible to prevent large induced voltages in the electrical connections. These large induced voltages occur during rapid changes in current conduction versus time and can cause solid state devices to improperly change state, from conducting to non-conducting or from non-conducting to conducting. High interconnection inductance increases the trigger system requirements and limits applications for the devices. Therefore, properly designed packages maximize electrical insulation while minimizing the electrical impedance and inductance of the electrical connections.
Another important issue for packaging solid state devices is to prevent the exposure of the solid state devices to an oxidizing environment, both during the packaging and in use. To prevent oxidation during packaging, the packaging environment is controlled by using vacuum or inert gas atmosphere. These conditions prevent oxidizing agents such as oxygen and water from affecting components during the packaging. To prevent oxidation after packaging, the packaging materials are selected to prevent the oxidizing agents from migrating to the components inside the package. For example, hardened encapsulants can act as a hermetic seal, significantly slowing the migration of oxygen and water to the components internal to the package. By reducing the exposure of the internal components to oxidizing agents, the lifetime of the components is greatly extended.